1. Field of the Invention
The present invention relates to a method for producing a crystalline silicon film that is formed on an insulating substrate such as a glass substrate, or a semiconductor substrate such as a single crystal silicon substrate, on which an insulating film is formed. In particular, the present invention relates to a method for obtaining a crystalline silicon film having a favorable crystalline state, comprising crystallizing an amorphous silicon film by means of annealing, in which lateral growth is allowed to occur on the amorphous silicon film by using a catalyst element (e.g., nickel) which accelerates the crystallization. Also, the invention relates to a method for manufacturing a semiconductor using such a crystalline silicon film.
2. Description of the Related Art
A crystalline silicon film that is formed on an insulating surface is indispensable for a semiconductor device such as a thin film transistor.
In general, a crystalline silicon film is obtained by crystallizing an amorphous silicon film by means of heating the amorphous silicon film or by irradiating laser light.
However, considering the electric properties, the crystalline silicon film obtained by heating or by irradiating a laser light is far inferior to a single crystal silicon wafer. Moreover, at present, a thin film transistor (referred to as a xe2x80x9cTFTxe2x80x9d) implemented by using such crystalline silicon films is also far inferior to a MOS-type transistor using a single crystal silicon wafer.
This is ascribed to the fact that the crystalline silicon film thus obtained contains defects at high density.
At present, the operation speed of a TFT consisting of a crystalline silicon film using an amorphous silicon film as the starting film is about several MHz or lower at best.
In contrast to above, an integrated circuit using a single crystal wafer having an operation speed of about 200 MHz is already put into practical use.
In case a technology generally known as SOI technology is employed, a MOS-type transistor having an operation speed exceeding the case of using a single crystal wafer is obtained because the capacitance is effectively reduced.
This technology comprises forming a single crystal layer on the silicon oxide layer by utilizing a single crystal silicon wafer. However, this technology is not practically feasible because of its disadvantages such that the size of the single crystal wafer is limited, and that it requires a complicated and costly manufacturing process.
According to the study of the present inventors, it is known that, by using particular kinds of metal elements which accelerate the crystallization of silicon, an amorphous silicon film can be modified into a high quality crystalline silicon film at a lower temperature and in a shorter duration of time.
The metal elements which accelerate the crystallization of silicon include nickel (Ni), platinum (Pt), palladium (Pd), copper (Cu), silver (Ag), and iron (Fe).
In particular, the direction of crystal growth can be controlled by non-selectively introducing such metal elements, and thus, silicon films having the preferred crystal structure suitable for devices can be obtained.
By employing such a technology, a TFT having characteristics well comparable to those of a MOS-type transistor using a single crystal silicon wafer can be realized (see Japanese Patent Application No. 8-335152 filed by the present inventors on Nov. 29, 1996).
This technology is denoted as xe2x80x9clateral growth methodxe2x80x9d. In a silicon film obtained by the lateral growth method, crystal grain boundaries are formed in parallel with the direction of growth; hence, by controlling the direction of electric current to be in parallel with the direction of crystal growth, the effect of the crystal grain boundaries can be reduced extremely. As a result, a polycrystalline material having characteristics well equivalent to those of a single crystal material can be realized.
The lateral growth method is described briefly below. The method comprises forming a mask film made of silicon oxide and the like on an amorphous silicon film, and forming selectively a window therein. A metal element, representatively nickel, which accelerates the crystallization of silicon, is introduced into the amorphous silicon film through this window. In FIG. 1A, a window is denoted by reference numeral 11.
As a method for introducing the metal element, there can be mentioned a method comprising depositing on a predetermined region of the amorphous silicon film, a film of a compound containing the metal element by means of sputtering (see Japanese Unexamined Patent Publication No. 7-45519 or 7-66425), a vapor growth method (Japanese Unexamined Patent Publication No. 7-335548), or a coating method (Japanese Unexamined Patent Publication No. 7-130652).
Then, by performing annealing for crystallization, the region of crystalline silicon (lateral growth region) 13 is expanded around the window. Such a region can be obtained because the catalyst element crystallizes the amorphous silicon film while it diffuses inside the silicon film. In general, crystallization proceeds farther for higher temperature and longer duration (see FIG. 1A; details are described in the unexamined patent publications mentioned above). This crystal growth is called lateral growth because it proceeds in the direction parallel with the film plane.
The properties of the semiconductor device can be improved by arranging the direction of lateral growth to match with the direction of current flow in semiconductor devices such as a thin film transistor (TFT). Specifically, TFTs can be arranged in a variety of ways. An example of such ways is shown in FIG. 3. Referring to FIG. 3, there is shown a crystallized region 302 obtained by lateral growth around a window portion 301 into which the catalyst element is added.
In such a case, an oval laterally grown region as shown in FIG. 3 can be obtained if a rectangular window 301 is provided. In this case, the gate electrode 304 is arranged approximately in parallel with the region 301 as is shown by TFT1, so that crystal growth may occur in a direction from drain 305 to source 303, or in the reversed direction.
Furthermore, as is shown in TFT2 of FIG. 3, there are cases in which the region 301 is arranged approximately vertical to the gate electrode 307, so that the crystal growth may occur approximately simultaneously with source 306 and drain 308. Thus, concerning the characteristics of the resulting TFT, high ON current is obtained when the former method is adopted because the crystal grain boundaries are arranged in a direction parallel to the direction of current flow. In contrast to this, a TFT with high OFF current results when the latter method is adopted, because the crystal grain boundaries are arranged in a direction vertical to the direction of current flow.
Otherwise, the window may be narrowed into a line so that the catalyst element is added linearly. FIGS. 4A and 4B show a case of a circuit provided with a plurality of TFTs, in which the regions 401 and 406 of catalyst element addition are formed in parallel with the gate lines 402 and 407. FIG. 4A corresponds to TFT2 shown in FIG. 3, which is the case of adding catalyst elements approximately vertical to the gate electrodes of the TFTs 403 to 405. FIG. 4B corresponds to TFT1 shown in FIG. 3, which is the case of adding catalyst elements approximately vertical to the gate electrodes of the TFTs 408 to 410.
Controlling the direction of crystal growth by using the lateral growth process is effective in sophisticated semiconductor integrated circuits in which devices having functions conflicting to each other are formed on a single substrate. FIG. 5 shows a block diagram of a monolithic active matrix circuit for use in liquid crystal displays. Referring to FIG. 5, a source driver (column driver) 501 and gate driver (row driver) 502 are provided as peripheral driver circuits. In the figure are also shown a video signal 503, a latch pulse 504, a shift register X 505, an analog memory 506, an analog switch 507, an analog buffer 508, and a shift register Y 509.
A large number of pixel circuits comprising transistors 511 and capacitors 512 for switching are formed in the active matrix circuit (pixel) region 510; the pixel transistors 511 of the active matrix circuit are connected with the peripheral driver circuit by the source lines and the gate lines corresponding to the number of rows and columns, respectively. In FIG. 5, a liquid crystal portion 513 is also shown. High speed operation is required for the TFTs that are used in the peripheral circuit, and particularly, for the peripheral logic circuits such as a shift register. To fulfill this requirement, it is required that the current when selected (ON current) is high, and that the scattering is small.
In contrast to above, TFTs for use in pixel circuits are required in which the charge accumulated in the capacitor can be retained for a longer duration of time. Accordingly, they should have a sufficiently low leak current (i.e., OFF current) when it is not selected, that is, the leak current is sufficiently low when reversed bias voltage is applied to the gate electrode, and in which the fluctuation thereof is small. More specifically, an OFF current of 1 pA or lower with a fluctuation within one digit is required. To the contrary, the ON current need not be so high.
As described above, TFTs having physical properties thus conflicting with each other, i.e., a high ON current and low leak current, yet, with small fluctuation in the value, are required to be formed on a single substrate. However, it can be readily understood that it is extremely difficult to technologically fulfill these requirements by an ordinary method of crystallization.
The problems above can be solved by controlling the direction of crystallization by employing lateral growth method (see Japanese Unexamined Patent Publication No. 8-213634). It is well known that lateral growth method using catalyst elements is effective.
Furthermore, the fluctuation in characteristics of devices can be minimized.
Moreover, TFTs manufactured by using the thus laterally grown region can be operated at a speed as high as several hundreds of megahertz (MHz) (see Japanese patent application No. 8-335152 filed by the present inventors on Nov. 29, 1996).
Still, problems were found on the control in distance of lateral growth and on the reliability of the resulting device characteristics.
To solve the problems above, intensive study has been carried out, and the following points have been found.
(1) It is sometimes found to generate a region comprising concentrated defects on the way of lateral growth, or a region in which lateral growth is apparently impaired.
(2) The TFTs manufactured by using the portions of such a state exhibit inferior device characteristics and low reliability.
Ideally, an infinitely large laterally growth can be obtained by performing annealing at a higher temperature and for a longer duration of time. In fact, however, although the laterally grown region expands, a plurality of portions of catalyst element precipitation are formed inside the expanded region. The catalyst elements are electrically conductive, and when they are etched, vacancies remain on the silicon film to cause defective circuits.
Thus, when an attempt is made to obtain a large laterally grown region, the quality of the crystal as a whole decreases due to the precipitation of the catalyst element. This is illustrated in FIG. 1B. FIG. 1B shows the state in which lateral growth continues from the state shown in FIG. 1A, and the region 13 of lateral growth expands to the portion shown by the oval 14 drawn by a solid line (In FIG. 1A, the portion is shown by an oval 12 drawn by broken lines).
However, particularly in the portion far from the window, a region in which catalyst element is precipitated (indicated by black dots 15 in FIG. 1B) appears.
In general, the window 11 and the region in vicinity thereof are high in catalyst element concentration, and are therefore preferred that the main portion of the device is manufactured without using these regions. Under the present technology level, in a lateral growth method using nickel as a catalyst element, the width of the lateral growth free from precipitation of nickel is from 50 to 60 xcexcm at maximum, but it is necessary to increase the lateral growth region in larger devices.
As a result of intensive study on this point, the precipitation of catalyst element has been found to occur due to the discontinuation of lateral growth attributed to spontaneous crystallization (generation of crystal nuclei and crystal growth which occurs without the function of catalyst element). In other words, it has been found that it occurred influenced by the spontaneous crystallization other than the crystallization using the function of the additional metal element.
In further detail, lateral growth using the function of a metal element was found to be greatly obstructed or halted when it reached the crystal growth region which proceeds spontaneously.
This has been found to be the cause of concentrating defects to a part of the lateral growth region or of realizing a state in which the lateral growth is obstructed, and also, a cause of fluctuation in the characteristics or instability in a TFT obtained.
An object of the present invention is to solve the aforementioned problems. More specifically, an object of the present invention is to provide annealing conditions which realizes a larger lateral growth region while reducing the precipitation of catalyst element.
According to an aspect of the present invention, it is characterized by crystallizing an amorphous silicon film by employing lateral growth method to perform annealing at temperature T0 using a catalyst element which accelerates the crystallization, provided that, the duration of annealing accounts for 90% or more but less than 100% of the time duration t0 necessary to crystalize at temperature T0 under the conditions of using no catalyst elements.
According to the present inventors"" observation, it has been found that the precipitation of catalyst elements occurs due to the discontinuation of lateral growth attributed to spontaneous crystallization of the amorphous silicon film. Hence, the precipitation of catalyst element can be suppressed by performing lateral growth under the conditions where no spontaneous crystallization occurs.
Given with the annealing temperature, the time at which spontaneous crystallization initiates can be specified. If annealing is carried out for a duration of time exceeding the specified range, catalyst elements precipitates by spontaneous crystallization. If the duration of annealing is too short, it results in an insufficient lateral growth. It is therefore preferred that the duration of time is limited to 90% or more but less than 100% of the time t0 when spontaneous crystallization initiates. However, there remains the possibility that a lateral growth region having a desired area cannot be obtained.
To overcome this problem, the annealing temperature and the duration of annealing are determined from the required width of lateral growth by setting the annealing temperature as a variable. More specifically, first, the relational expression between the annealing temperature and the duration of annealing at the critical conditions in spontaneous crystallization as follows is obtained:
t=f(T)
where, T represents the annealing temperature and t represents the duration of annealing.
For example, in case an amorphous silicon film formed by plasma CVD is annealed at 600xc2x0 C., spontaneous crystallization occurs in 4 hours. Similar data is obtained for other temperatures and the results are shown, for instance, in a graph of FIG. 1C. In FIG. 1C, the abscissa shows the temperature, and the ordinate represents the time duration.
In general, different curves are obtained depending on the manufacturing process of an amorphous silicon film. For instance, an amorphous silicon film obtained by plasma CVD (solid lines in FIG. 1C, indicated by Si-film b) can be crystallized more easily than one obtained by low pressure CVD (dotted lines in FIG. 1C, indicated by Si-film a); thus, the curve for the former is located at lower left of the curve for the latter.
Then, the relational expression between the annealing temperature and the growth distance as follows is obtained for lateral growth:
x=g(T, t)
where, x represents the growth distance. This can be seen, for example, in FIG. 1D. In the graph of FIG. 1D, the growth rate expressed in the ordinate is shown by logarithmic scale, whereas the abscissa represents the reciprocal of the temperature (1/(temperature)).
Thus, for a given desired growth distance x0, critical time duration of annealing t0 and critical annealing temperature T0 can be obtained as values satisfying the relation above.
In fact, a crystalline silicon film almost free of any precipitates of catalyst element can be obtained for a desired lateral growth distance by performing annealing at any temperature not higher than the critical annealing temperature T0 described above. By further continuing the annealing, precipitation of catalyst element occurs with the occurrence of spontaneous crystallization on the outside of the laterally grown region. However, there is no problem if the portion at which spontaneous crystallization has occurred is not important for the desired circuit. Thus, this method allows lateral crystallization to occur to a desired distance with few precipitation of catalyst metal. More preferably, the duration of annealing and the annealing temperature fall in a range of 90% or more and less than 100% of the critical time duration of annealing and critical annealing temperature.
In the present invention, the critical conditions of spontaneous crystallization can be measured (or determined) effectively by observation using optical microscope or electron microscope, or by a spectroscopic means (such as Raman spectroscopy). However, it should be noted that the relational expression obtained is not universal; that is, the relation differs depending on the determination methods. Thus, the critical annealing duration and the critical annealing temperature differs depending on the method of determining spontaneous crystallization.
Furthermore, the relation between the temperature and the duration of time changes with changing conditions in spontaneous crystallization as well as in lateral growth. The conditions include the substrate and base film, the thickness of the amorphous silicon film and the method of forming the film, cap film (mask film), etc. Thus, in case of determining the relation function g, the same conditions used in forming the amorphous silicon film must be employed. In case of determining the relation function f, it is effective to cover the amorphous silicon film with a mask film that is used in lateral growth of the amorphous silicon film.
It is also known that the temperature at which the crystallization proceeds in case the metal element is used to accelerate the crystallization of silicon differs from the temperature at which crystallization occurs spontaneously. More specifically, the temperature T2 of spontaneous crystallization is higher than the temperature T1 of the crystallization accelerated by the use of a metal element.
Thus, by allowing the lateral growth to occur under properly set conditions at which spontaneous crystallization does not proceed, lateral growth can be proceeded smoothly. More specifically, the negative influence of spontaneous crystallization on lateral growth can be suppressed by allowing lateral growth to occur at a temperature at which spontaneous crystallization does not proceed (i.e., the temperature at which spontaneous nucleation does not take place or can be neglected).
FIG. 8 shows a graph obtained by plotting the nucleation ratio (ordinate) for each of the heat treatment temperatures (abscissa) in case of crystallizing an amorphous silicon film obtained by low pressure thermal CVD (LPCVD), in which nickel is used as the catalyst element. The sample was prepared in accordance with the process described hereinafter in Example 2. The term xe2x80x9cnucleixe2x80x9d used in xe2x80x9cnucleation ratioxe2x80x9d herein signifies the xe2x80x9cnuclei obtained in spontaneous crystallizationxe2x80x9d, and it refers to the initial stage of spontaneous crystallization.
The nucleation ratio shown in FIG. 8 is obtained by selecting a region free from the influence of nickel, and observing it using an optical micrograph.
According to the knowledge of the present inventors, lateral growth is evaluated free from the influence of spontaneous crystallization if the generation ratio of spontaneously generated nuclei in an area of 1 xcexcm2 is 10xe2x88x922 nuclei or less per 1 hour.
In case the starting film is formed by low pressure thermal CVD (LPCVD), referring to FIG. 8, a heat treatment temperature at which the spontaneous nucleation ratio in an area of 1 xcexcm2 is not higher than 10xe2x88x922 nuclei per hour.
Referring to FIG. 8, the value of the abscissa for a spontaneous nucleation ratio of 10xe2x88x922 can be read as 1.166. Thus, by calculating 1000/(t+273)=1.166, t=585xc2x0 C. can be obtained. That is, in case the starting film is formed by low pressure thermal CVD (LPCVD), the spontaneous nucleation ratio in an area of 1 xcexcm2 can be suppressed to 10xe2x88x922 nuclei or less per hour by setting the heating temperature to 585xc2x0 C. or lower during crystallization.
The heat treatment temperature for a spontaneous nucleation ratio of 10xe2x88x922 in case the starting film is formed by PCVD can be obtained by calculating similarly as above. Thus, by calculating 1000/(t+273)=1.2025, t=559xc2x0 C. can be obtained. That is, in case the starting film is formed by plasma CVD (PCVD), the spontaneous nucleation ratio in an area of 1 xcexcm2 can be suppressed to 10xe2x88x922 nuclei or less per 1 hour by setting the heating temperature to 559xc2x0 C. or lower during crystallization.
In contrast to above, the rate of lateral growth (growth distance per unit of time) can be lowered by decreasing the heating temperature while performing crystallization.
When manufacturing an integrated circuit, it is desired to obtain a lateral growth distance of about 100 xcexcm. The duration of heat treatment is preferably 50 hours or less (as a matter of course, the shorter time duration is preferable from the viewpoint of operation efficiency).
To satisfy the conditions above, it is required to complete the heat treatment of a crystal growth distance of 100 xcexcm within 50 hours. Thus, a speed of lateral growth of 2 xcexcm or higher is required.
FIG. 9 shows the relation between the rate of lateral growth (ordinate) and the heat treatment temperature (abscissa). The sample can be manufactured in accordance with the process described in Example 2.
Referring to FIG. 9, the rate of lateral growth is clearly dependent on the heating temperature. That is, the rate of lateral growth is higher for a higher heating temperature, and the lateral growth is more sluggish for a lower heating temperature. Furthermore, it can be read that the temperature dependence of growth rate differs depending on which film to be used as the starting material; i.e., whether a LPCVD film or a PCVD film is selected.
However, in fact, it is believed that the temperature dependence of the lateral growth rate is attributed to the quantity of nickel introduced for the crystallization, and not to the film quality (the difference in the method of forming the film). The reason is that the difference in plotted points shown in FIG. 9 reflects the difference in concentration of nickel (i.e., nickel concentration in nickel acetate) introduced into the film.
Furthermore, from experimental results, it is known that there is almost no difference in growth rate depending on film quality (the difference in the method of forming the film) when the nickel concentration of nickel acetate is not changed.
Accordingly, it can be concluded that the difference in growth rate is attributed to the difference in the quantity of nickel introduced into the film. Accordingly, FIG. 9 shows the temperature dependence of lateral growth rate reflecting the difference in the quantity of nickel introduced into the film.
The heat treatment temperature in the case where lateral growth rate is 2 xcexcm/hr can be obtained from FIG. 9. The plots obtained for a sample crystallized by using a nickel acetate solution containing 100 ppm nickel is used in this case.
First, the straight line (solid line shown in FIG. 9) obtained by connecting the plots is extrapolated until it crosses a straight line which passes a point of 2 xcexcm/hr in the ordinate with gradient of 0 (i.e., a straight line in parallel with the abscissa), and the coordinates for the crossing point are obtained. Thus, the value for T is obtained from the coordinates to result in an equation of (1000/T)=1.248. Because T=273+t, t can be calculated as 528xc2x0 C.
That is, to maintain a growth rate of 2 xcexcm/hr or higher, it is concluded that a heating temperature of 528xc2x0 C. or higher should be fulfilled during crystallization. This temperature is independent to the film forming process.
Furthermore, when the concentration of nickel to be introduced is reduced to {fraction (1/10)}, a temperature of 536xc2x0 C. is obtained by using the straight line connecting the plots for 10 ppm in FIG. 9. That is, the straight line (dotted lines shown in FIG. 3) obtained by connecting the plots is extrapolated until it crosses a straight line which passes a point of 2 xcexcm/hr in the ordinate with gradient of 0 (i.e., a straight line in parallel with the abscissa), and the coordinates for the crossing point are obtained. Thus, the value for T is obtained from the coordinates to result in an equation of (1000/T)=1.236. Because T=273+t, t can be calculated as 536xc2x0 C.
To conduct a practical lateral growth, the concentration of nickel in nickel acetate solution should be 10 ppm or higher. Conclusively, to obtain a growth rate of 2 xcexcm/hr or higher, a heating temperature at crystallization of 536xc2x0 C. or higher is required.
The same holds true in the case where other means are used to introduce nickel into the film. Furthermore, as a matter of course, the heat treatment temperature can be elevated in the case where the quantity of nickel introduced into the film is increased.
From the discussion above, it can be concluded as follows in case low pressure thermal CVD (LPCVD) is employed for the formation of the starting film. The heat treatment temperature should be selected from a range of from 536 to 585xc2x0 C. to satisfy the conditions of:
(1) Suppressing spontaneous nucleation, and.
(2) Maintaining the lateral growth rate of 2 xcexcm/hr or higher.
Then, in case plasma CVD (PCVD) is used for the formation of the starting film, it is concluded that the heat treatment temperature should be selected from a range of from 536 to 559xc2x0 C. to satisfy the conditions of:
(1) Suppressing spontaneous nucleation, and.
(2) Maintaining the lateral growth rate of 2 xcexcm/hr or higher.
The maximum growth rate obtained under a state of suppressing spontaneous nucleation is calculated from FIG. 3. When LPCVD film is used for the starting film, the rate is less than 20 xcexcm/hr, and for PCVD film, it is higher than 7 xcexcm/hr.
That is, in case of a LPCVD film, T=858 K is obtained for t=585xc2x0 C. from T=(t+273), and the coordinate corresponding to the abscissa in FIG. 9 is 1.166, from which rate is read as less than 20 xcexcm/hr from FIG. 9.
On the other hand, in case of a PCVD film, T=832 K is obtained for t=559xc2x0 C. from T=(t+273), and the coordinate corresponding to the abscissa in FIG. 9 is 1.202, from which rate is read as higher than 7 xcexcm/hr from FIG. 9.
In the calculation above, the maximum growth rate is to be obtained. Accordingly, plots (solid line) for a nickel concentration of 100 xcexcm must be used.
When higher productivity is required, preferably, a lateral growth distance of 100 xcexcm should be achieved in about 25 hours. In such a case, the growth distance of about 4 xcexcm/hr is required. The lower limit of the heat treatment temperature under such a condition is 545xc2x0 C.
That is, by taking the solid line (for a case the quantity of nickel introduced is high) in FIG. 9 into consideration, the value corresponding in the abscissa corresponding to 4 xcexcm/hr is 1.223. Thus, the corresponding temperature is 545xc2x0 C. That is, to achieve a growth rate of 4 xcexcm/hr or higher, the heating temperature should be 545xc2x0 C. or higher.
In case the quantity of nickel introduced into the film is lowered, the lower limit of the heating temperature becomes more higher. For instance, referring to the dotted lines (for a case the quantity of nickel introduced is low) in FIG. 9, the value corresponding in the abscissa corresponding to 4 xcexcm/hr is 1.212. Thus, the corresponding temperature is 552xc2x0 C. That is, to achieve a lateral growth rate of 4 xcexcm/hr or higher, the heating temperature should be 552xc2x0 C. or higher in a minimum quantity of nickel introduced.
Thus, from the discussion above, according to an aspect of the present invention, there is provided a method for manufacturing a semiconductor comprising the steps of:
forming an amorphous silicon film on an insulating surface by means of low pressure thermal CVD process;
selectively introducing nickel element into a partial area of the amorphous silicon film; and
applying heat treatment and thereby allowing crystal growth to occur in a direction parallel to a film plane from the area into which the nickel element is selectively introduced;
wherein the heat treatment is performed in a temperature range of from 536 to 585xc2x0 C., and the crystal growth is performed in a rate of from 2 xcexcm/hr to 20 xcexcm/hr.
Further according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor comprising the steps of:
forming an amorphous silicon film on an insulating surface by means of plasma CVD process;
selectively introducing nickel element into a partial area of the amorphous silicon film; and
applying heat treatment and thereby allowing crystal growth to occur in a direction parallel to the film plane from the area into which the nickel element is selectively introduced,
wherein the heat treatment is performed in a temperature range of from 536 to 559xc2x0 C., and the crystal growth is performed in a rate of from 2 xcexcm/hr to 7 xcexcm/hr.
By adopting the constitution above, the spontaneous nucleation during heat treatment can be suppressed to 10xe2x88x922 nuclei/hr or less for an area of 1 xcexcm2.
The present invention can be applied to manufacturing of a semiconductor itself, or to manufacturing of TFTs and thin film integrated circuits, or to devices using the same, such as personal handyphone systems and computers.
As substrates having insulating surfaces, included are glass substrates, quartz substrates, semiconductor substrates on which insulating films are formed, alumina/glass substrates, etc.
The most simple method for selectively introducing nickel element into the film is the one using a solution as is described hereinafter. However, nickel element may be introduced selectively into a part of the amorphous silicon film by using methods such as ion implantation, plasma treatment (discharge treatment using an electrode containing nickel), sputtering, CVD process, gas adsorption method, etc.
To allow crystal growth to proceed in a direction in parallel with the film plane from the region into which nickel is introduced selectively signifies to allow crystal growth to proceed in a direction in parallel with the substrate (denoted as xe2x80x9clateral growthxe2x80x9d) as is shown by numeral 10 in FIG. 7B.
The term a xe2x80x9cspontaneous nucleusxe2x80x9d signifies a crystal nucleus that is formed in the initial stage of nucleation which proceeds spontaneously by heat treatment without using any nickel. This can be observed by using an optical microscope.
The constitution of the invention is based on experimental data. Accordingly, in practical use, an allowance of (xc2x15xc2x0 C. is preferably included in the limits of temperature range.
Thus, in case an amorphous silicon film formed by low pressure thermal CVD (LPCVD) is used as the starting film, the requirements such as achieving lateral growth free from influence of crystal growth attributed to spontaneous nucleation and a practically feasible growth rate from the view point of a manufacturing process can be fulfilled by:
controlling the temperature of the heat treatment to fall in a range of form 536 to 585xc2x0 C.; and
controlling the crystal growth rate to a range of from 2 to 20 xcexcm/hr; thereby suppressing spontaneous nucleation rate to 10xe2x88x922 nuclei/hr or less for an area of 1 xcexcm2.
Furthermore, in case an amorphous""silicon film formed by plasma CVD (PCVD) is used as the starting film, the requirements such as achieving lateral growth free from influence of crystal growth attributed to spontaneous nucleation and a practically feasible growth rate from the view point of a manufacturing process can be fulfilled by:
controlling the temperature of the heat treatment to fall in a range of form 536 to 559xc2x0 C.; and
controlling the crystal growth rate to a range of from 2 to 7 xcexcm/hr;
thereby suppressing spontaneous nucleation rate to 10xe2x88x922 nuclei/hr for an area of 1 xcexcm2.